1. Field of the Invention
The present invention generally relates to the testing of circuits, and, more specifically, to testing the data transmission performance of circuits that transmit and/or receive high speed, serial data.
2. Description of Related Art
As the data rate of IC pins increases each year, well beyond a few gigahertz, it becomes necessary to consider embedding test capabilities in an integrated circuit (IC) so that a tester will not need to operate accurately at the data rate being tested.
In automatic test equipment (ATE), it is common to include a parametric measurement unit (PMU) to measure the drive of an IC's output pin, or to accurately deliver a DC voltage. The output drive of a pin is tested by applying a known current to the pin and measuring the resultant voltage at the pin, or by applying a known voltage and measuring the resultant current. As shown in FIG. 1, a DC voltage 10 is accurately delivered to a pin 12 of an IC 14 by applying (forcing) a voltage via a first conductive path 16 of the test equipment 20 and sensing the applied voltage via a second conductive path 18 of the test equipment. Typically, an operational amplifier 22 is used to adjust the applied voltage until the sensed voltage is equal to the desired voltage. The “conductive paths” typically comprise wires, board-to-board interface connectors, and electromechanical relays. Although a PMU can deliver and measure a signal accurately, it is only suitable for DC or very low frequencies.
A standard entitled “IEEE Standard for a Mixed Signal Test Bus”, was published in 1999 by the IEEE, and is known as IEEE Std. 1149.4-1999, or simply 1149.4. The general architecture of an IC designed according to 1149.4 is shown in FIG. 2. This test bus was primarily designed to permit the measurement of discrete passive components, including capacitors and resistors, that are connected to the pins of ICs. It is intended for applying a stimulus current or voltage to a pin, via one of these test buses, AB1 or AB2, and simultaneously monitoring the pin's response voltage via another, AB2 or AB1, of these test buses, and to thus determine the impedance of a circuit that has been connected to a pin. A boundary scan cell 24 for an individual pin 12 is shown in FIG. 3. 1149.4 offers a way to embed test capabilities in an IC, but it is only practical for fairly low frequencies, much lower than the gigahertz rate at which some ICs transmit signals.
A primary difficulty in testing gigahertz signals is maintaining signal integrity when accessing the signals. The typical way of improving the signal integrity of a transmission line is to terminate it with an impedance RL equal to the characteristic impedance of the transmission line. In the case of differential signals, the termination resistor is typically connected between the differential signals and has a value equal to twice the characteristic impedance (typically 50 ohms) of individual the transmission lines. Low voltage differential signaling (LVDS) circuits typically use a differential current driver and terminate the differential pair at the receiver with a three-resistor combination that is intended to provide a small constant voltage offset to the differential signal so that if one of the signal wires is open circuit, the input to the receiver will appear to have a constant voltage and appear as a constant logic value instead of being intermittent.
A variety of termination and biasing circuits are possible—some commonly used circuits are shown in FIGS. 4A, 4B, 4C, and 4D. AC coupling allows the common mode (average) voltage of the received signal to be optimized for the receiver, independent of the transmitted common mode voltage.
Another standard is entitled, “IEEE 1149.6: Standard for Boundary-Scan Testing of Advanced Digital Networks”, describes a method for testing differential signals that are AC-coupled.
Bit error rate testing is a common way of testing the performance of a digital communication system. Typical high frequency signals (greater than 1 Gb/s) achieve a bit error rate (BER) better than 1 in 1012 bits. To test this performance it is necessary to test at least 1012 bits, and at 1 Gb/s this can take 1000 seconds, which is too long for production testing. Some circuits are simply tested for less than one second to verify that no bit errors are detected, but this is not a very thorough test. A prior art method to make a short duration BER test more meaningful is to inject noise or jitter. This is sometimes referred to as “stressed eye” testing.
A prior art method for injecting data dependent jitter into a high speed serial bit stream was published in Design & Test January 2002, and is entitled, “Jitter Testing for Gigabit Serial Communication Transceivers”, by Yi Cai et al. To test a data path, a differential signal drives a series resistance and a capacitor is connected across the differential output which is then looped back into a differential input. This has the effect of injecting data dependent jitter because the mid-level crossing time depends on the preceding number of ones and zeroes, as shown in FIG. 5. However, the capacitor value might need to be very accurate and very small: for a 2.5 Gb rate, the unit interval (UI) is 400 ps, so using the standard 100 ohm termination resistor, and setting RC=1 UI, then C must equal 400 ps/100 ohms=4 pF, which is equal to the typical capacitance of one or two centimeters of wire on a printed circuit board, and is very sensitive to any stray capacitances.